Semiconductor processing method, method of forming DRAM circuitry, method of depositing a tungsten comprising layer over a substrate, method of forming a transistor gate line over a substrate, method of forming a patterned substantially crystalline Ta2O5 comprising material, and method of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material

ABSTRACT

In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta 2 O 5  comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta 2 O 5  comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta 2 O 5  comprising layer over a semiconductive substrate. The layer is exposed to WF 6  under conditions effective to etch substantially amorphous Ta 2 O 5  from the substrate. In one implementation, the layer is exposed to WF 6  under conditions effective to both etch substantially amorphous Ta 2 O 5  from the substrate and deposit a tungsten comprising layer over the substrate during the exposing.

TECHNICAL FIELD

[0001] The invention relates to semiconductor processing methods, tomethods of forming DRAM circuitry, to methods of depositing a tungstencomprising layer over a substrate, to methods of forming a transistorgate line over a substrate, to methods of forming a transistor gate lineover a substrate, to methods of forming a patterned substantiallycrystalline Ta₂O₅ comprising material, and to methods of forming acapacitor dielectric region comprising substantially crystalline Ta₂O₅comprising material.

BACKGROUND OF THE INVENTION

[0002] As DRAMs increase in memory cell density, there is a continuingchallenge to maintain sufficiently high storage capacitance despitedecreasing cell area. Additionally, there is a continuing goal tofurther decrease cell area. One principal way of increasing cellcapacitance is through cell structure techniques. Such techniquesinclude three-dimensional cell capacitors, such as trenched or stackedcapacitors. Yet as feature size continues to become smaller and smaller,development of improved materials for cell dielectrics as well as thecell structure are important. The feature size of 256 Mb DRAMs andbeyond will be on the order of 0.25 micron or less, and conventionaldielectrics such as SiO₂ and Si₃N₄ might not be suitable because of lowdielectric constants.

[0003] Highly integrated memory devices are expected to require a verythin dielectric film for the 3-dimensional capacitor of cylindricallystacked or trench structures. To meet this requirement, the capacitordielectric film thickness will be below 2.5 nm of SiO₂ equivalentthickness.

[0004] Insulating inorganic metal oxide materials (such as ferroelectricmaterials, perovskite materials and pentoxides) are commonly referred toas “high k” materials due to their high dielectric constants, which makethem attractive as dielectric materials in capacitors, for example forhigh density DRAMs and non-volatile memories. Using such materialsenable the creation of much smaller and simpler capacitor structures fora given stored charge requirement, enabling the packing density dictatedby future circuit design. One such material is tantalum pentoxide.

[0005] Tungsten, in desired elemental or compound forms, is a conductivematerial finding increasing use in the fabrication of circuit devices.The semiconductor industry continues to search for new and hopefullyimproved ways of depositing or otherwise forming tungsten materials ontoa substrate.

SUMMARY

[0006] The invention comprises semiconductor processing methods, methodsof forming DRAM circuitry, methods of depositing a tungsten comprisinglayer over a substrate, methods of depositing an elemental tungstencomprising layer over a substrate, methods of depositing a tungstennitride comprising layer over a substrate, methods of depositing atungsten silicide comprising layer over a substrate, methods of forminga transistor gate line over a substrate, methods of forming a patternedsubstantially crystalline Ta₂O₅ comprising material, and methods offorming a capacitor dielectric region comprising substantiallycrystalline Ta₂O₅ comprising material. In one implementation, asemiconductor processing method includes forming a substantiallyamorphous Ta₂O₅ comprising layer over a semiconductive substrate. Thelayer is exposed to WF₆ under conditions effective to etch substantiallyamorphous Ta₂O₅ from the substrate. In one implementation, the layer isexposed to WF₆ under conditions effective to both etch substantiallyamorphous Ta₂O₅ from the substrate and deposit a tungsten comprisinglayer over the substrate during the exposing. In one implementation,aspects of the invention are used to fabricate a transistor gate line.In one implementation, aspects of the invention are used to fabricateDRAM circuitry.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0008]FIG. 1 is a diagrammatic sectional view of a semiconductor waferfragment at one processing step in accordance with an aspect of theinvention.

[0009]FIG. 2 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 1.

[0010]FIG. 3 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 1 and alternate to that shown by FIG.2.

[0011]FIG. 4 is a diagrammatic sectional view of an alternate embodimentsemiconductor wafer fragment at a processing step in accordance with anaspect of the invention.

[0012]FIG. 5 is a view of the FIG. 4 wafer fragment at a processing stepsubsequent to that shown by FIG. 4.

[0013]FIG. 6 is a view of the FIG. 4 wafer fragment at a processing stepsubsequent to that shown by FIG. 5.

[0014]FIG. 7 is a diagrammatic sectional view of yet another alternateembodiment semiconductor wafer fragment at a processing step inaccordance with an aspect of the invention.

[0015]FIG. 8 is a view of the FIG. 7 wafer fragment at a processing stepsubsequent to that shown by FIG. 7.

[0016]FIG. 9 is a view of the FIG. 7 wafer fragment at a processing stepsubsequent to that shown by FIG. 8.

[0017]FIG. 10 is a view of the FIG. 7 wafer fragment at a processingstep subsequent to that shown by FIG. 9.

[0018]FIG. 11 is a diagrammatic sectional view of still anotheralternate embodiment semiconductor wafer fragment at a processing stepin accordance with an aspect of the invention.

[0019]FIG. 12 is a view of the FIG. 11 wafer fragment at a processingstep subsequent to that shown by FIG. 11.

[0020]FIG. 13 is a view of the FIG. 11 wafer fragment at an alternateprocessing step to that shown by FIG. 12.

[0021]FIG. 14 is a view of the FIG. 11 wafer fragment at a processingstep subsequent to that shown by FIG. 12.

[0022]FIG. 15 is a diagrammatic sectional view of another alternateembodiment semiconductor wafer fragment at a processing step inaccordance with an aspect of the invention.

[0023]FIG. 16 is a view of the FIG. 15 wafer fragment at a processingstep subsequent to that shown by FIG. 15.

[0024]FIG. 17 is a view of the FIG. 15 wafer fragment at a processingstep subsequent to that shown by FIG. 16.

[0025]FIG. 18 is a view of the FIG. 15 wafer fragment at a processingstep subsequent to that shown by FIG. 17.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0027] Referring to FIG. 1, a semiconductive substrate is indicatedgenerally with reference numeral 10, and comprises bulk monocrystallinesilicon 12. In the context of this document, the term “semiconductorsubstrate” or “semiconductive substrate” is defined to mean anyconstruction comprising semiconductive material, including, but notlimited to, bulk semiconductive materials such as a semiconductive wafer(either alone or in assemblies comprising other materials thereon), andsemiconductive material layers (either alone or in assemblies comprisingother materials). The term “substrate” refers to any supportingstructure, including, but not limited to, the semiconductive substratesdescribed above. Also in the context of this document, the term “layer”includes both the singular and the plural unless otherwise indicated.

[0028] A substantially amorphous Ta₂O₅ layer 14 is formed over substrate12. The preferred method for forming layer 14 is by chemical vapordeposition, for example, using Ta(OC₂H₅)₅ and O₂ as precursors at anexemplary susceptor temperature range from 400° C. to 550° C. and anexemplary ambient pressure from 100 mTorr to 20 Torr. Further in thepreferred embodiment, layer 14 preferably consists essentially ofsubstantially amorphous Ta₂O₅. In the context of this document,“substantially amorphous” means at least 95% amorphous phase whereas“substantially crystalline” means at least 95% crystalline phase.

[0029] Referring to FIG. 2, layer 14 has been exposed to WF₆ underconditions effective to etch substantially amorphous Ta₂O₅ from thesubstrate. In the illustrated and preferred example, such exposing iseffective to etch substantially all of the substantially amorphous Ta₂O₅comprising layer from the substrate, although less than total removalis, of course, contemplated. Preferred conditions comprise a temperatureof at least 350° C., and more preferably a temperature of at least 400°C. Pressure is preferably subatmospheric, with an exemplary preferredrange being from 5 mTorr to 10 Torr. In one preferred embodiment, theexposing comprises an atmosphere which consists essentially of WF₆. Anexemplary flow rate in a 6-liter reactor is from 100 sccm to 500 sccm.An exemplary etch rate at about 400° C. and 5 Torr at this flow rate isfrom about 10 to 50 Angstroms/minute. Reduction to practice under suchconditions evidenced etching of substantially amorphous Ta₂O₅ with noappreciable etching of substantially crystalline Ta₂ 0 ₅. Accordingly inthe preferred embodiment, the subject etching is “substantiallyselective” relative to any presence of crystalline Ta₂O₅ on thesubstrate which, in the context of this document, means an etch rate ofat least 3:1, with significantly greater selectivity having beenachieved (i.e., on the order of 1000:1). Carrier or other reactive ornon-reactive gasses might be utilized. Any of the processing describedherein might be conducted with or without plasma, either remotely orwithin the chamber in which the substrate is received.

[0030] Etching alone of the Ta₂O₅ layer might occur, or a combination ofetching and deposition of a material commensurate with etching. In oneembodiment, provision of hydrogen (in H₂ or other form) within thechamber during processing can result in deposition of tungsten or atungsten compound in addition to etching of amorphous Ta₂O₅. Converselyin one embodiment, absence of hydrogen (in H₂ or other form) within thechamber during processing can result in etching of amorphous Ta₂O₅without deposition of tungsten or a tungsten compound.

[0031]FIG. 3 illustrates an alternate embodiment to that depicted byFIG. 2. Here, layer 14 (FIG. 1) has been exposed to WF₆ under conditionseffective to both etch substantially amorphous Ta₂O₅ from the substrateand deposit a tungsten comprising layer 16 over the substrate during theexposing. In the illustrated and preferred embodiment, the exposing iseffective to etch substantially all of the substantially amorphous Ta₂O₅comprising layer 14 from the substrate. In one preferred embodiment,tungsten comprising layer 16 comprises elemental tungsten, and in oneembodiment preferably consists essentially of elemental tungsten. In onepreferred exemplary process for etching and forming the same, the Ta₂O₅layer is exposed to WF₆ and hydrogen, whether in certain compound,bimolecular or other form. An example process is to flow H₂ to thereactor in a same or different stream from the WF₆, with an exemplary H₂flow rate being from about 100 sccm to about 1000 sccm. A preferredmethod of providing the hydrogen to the etching reactor is by firstsubjecting the hydrogen to a remote plasma such that the hydrogen fed tothe reactor for the etching and deposition is in an activated state.Temperature and pressure conditions are otherwise preferably asdescribed above with respect to the first described embodiment.

[0032] In one preferred embodiment, tungsten comprising layer 16comprises a conductive tungsten compound, and preferably consistsessentially of a conductive tungsten compound. One example preferredmaterial is tungsten nitride. Such can be formed by exposing layer 14 toWF₆ and nitrogen under conditions effective to both etch substantiallyamorphous Ta₂O₅ from the substrate and deposit a tungsten nitridecomprising layer over the substrate during the exposing. Example formsof nitrogen during the exposing include NH₃, N₂, N₂ plasma (eitherremote or within the chamber) and N₂H₂. Temperature and pressure areotherwise preferably as provided above in the first describedembodiment.

[0033] By way of example only, another example for layer 16 comprisestungsten silicide. One preferred technique for forming the samecomprises exposing the Ta₂O₅ layer to WF₆ and a silane under conditionseffective to both etch substantially amorphous Ta₂O₅ from the substrateand deposit a tungsten silicide comprising layer over the substrateduring the exposing. By way of example only, exemplary silanes includeSiH₄, disilane and dichlorosilane. Temperature and pressure conditionsare preferably as described above. For dichlorosilane, the substratetemperature is preferably at least 500° C.

[0034] In one preferred embodiment, tungsten comprising layer 16consists essentially of elemental tungsten, a conductive tungstencompound or mixtures thereof.

[0035] Reduction-to-practice examples showed depositing of a tungstencomprising layer in the above manner resulted in a higher depositionrate, better uniformity and better adhesion to underlying oxide materialbeneath the Ta₂O₅ than if the Ta₂O₅ was not there in the first place.Yet, the invention is in no way limited to these advantageous resultsunless specifically recited in an accompanying claim.

[0036] In but one aspect, a preferred implementation of the inventioncomprises a method of forming a transistor gate line over a substrate. Apreferred embodiment is described with reference to FIGS. 4-6. FIG. 4depicts a substrate 20 comprised of a bulk monocrystalline siliconsubstrate 22. A gate dielectric layer 24, for example silicon dioxide,is formed over semiconductive substrate 22. A conductively dopedsemiconductive material 26, for example n-type doped polysilicon, isformed over, and preferably on as shown, gate dielectric layer 24. Asubstantially amorphous Ta₂O₅ comprising layer 28 is formed over, andpreferably on as shown, conductive semiconductive material 26.

[0037] Referring to FIG. 5, substantially amorphous Ta₂O₅ comprisinglayer 28 (FIG. 4) has been exposed to WF₆ under conditions effective toboth remove substantially all of the substantially amorphous Ta₂O₅ fromthe substrate and deposit a conductive tungsten comprising layer 30 inits place over and in electrical connection with conductivesemiconductive material 26. Exemplary and preferred processing is asdescribed above.

[0038] Referring to FIG. 6 and after such exposing, at least tungstencomprising layer 30 and conductive semiconductive material 26 arepatterned into a transistor gate line 32. Preferred patterning is byphotolithography masking and etch.

[0039] In but yet another exemplary implementation, a method of DRAMcircuitry fabrication is described initially with reference to FIGS.7-10. Referring to FIG. 7, a wafer fragment 110 comprises two memorycells in fabrication, with each comprising a memory cell storagecapacitor 112. Capacitors 112 electrically connect with substratediffusion regions 118 through polysilicon plug regions 116. Diffusionregions 118 constitute pairs of source/drain regions for individualfield effect transistors. Individual storage capacitors 112 comprise afirst capacitor electrode 120 in electrical connection with one of apair of source/drain regions 118 of one field effect transistor. Acapacitor dielectric region 122 comprising substantially amorphousTa₂O₅, and preferably consisting essentially thereof, is received overfirst capacitor electrode 120 and an oxide layer 119 within which firstcapacitor electrodes 120 are received. Second capacitor cell electrodelayer 124 is formed over capacitor dielectric region 122.

[0040] Referring to FIG. 8, etching is conducted through a capacitorcell electrode layer 124 and capacitor dielectric layer 122 over theillustrated central source/drain region 118 to which ultimate bit lineelectrical connection is desired.

[0041] Referring to FIG. 9 and after the FIG. 8 etching, exposedportions of capacitor dielectric layer 122 are exposed to WF₆ underconditions effective to etch substantially amorphous Ta₂O₅ to recesscapacitor dielectric layer 122 relative to capacitor cell electrodelayer 124. Ta₂O₅ capacitor dielectric layers can undesirably result incurrent leakage to subsequent bit contacting plug material, with thesubject recessing preferably providing better separation between a bitcontact and the amorphous Ta₂O₅.

[0042] Referring to FIG. 10, an insulating layer 126 is formed over cellelectrode layer 124. Suitable patterning and etching is then conductedthrough layers 126 and 119 to provide an exposed contact for makingultimate electrical connection with the illustrated central source/draindiffusion region 118. A bit line 128 of an array of bit lines issubsequently fabricated, providing a bit contact 114 to the illustratedcentral source/drain region 118. An array of word lines 130 isfabricated to constitute gates of individual field effect transistors toenable selective gating of the capacitors relative to bit contact 114.

[0043] In still but another exemplary implementation, a method offorming a patterned substantially crystalline Ta₂O₅ comprising materialis described with reference to FIGS. 11-14. Referring initially to FIG.11, an exemplary substrate 40 comprises a bulk substrate 42. Asubstantially amorphous comprising Ta₂O₅ material is formed oversubstrate 42.

[0044] Referring to FIG. 12, a masking layer 46 is formed oversubstantially amorphous comprising Ta₂O₅ material 44. Exemplarymaterials for masking layer 46 include photoresist deposited toexemplary thicknesses of from 1,000 Angstroms to 50,000 Angstroms, andreflective materials such as metals (i.e., Al, Cu, Pt and others)deposited to an exemplary thickness of 100 Å to 10000 Å underline. Atleast one opening 48 is formed through masking layer 46 in a desiredpattern. A laser is applied, as depicted by the vertical down arrows, tosubstantially amorphous comprising Ta₂O₅ material 44 through opening 48in masking layer 46, and thereby is provided in the desired patterndepicted by opening 48. The laser application is effective to transformsubstantially amorphous comprising Ta₂O₅ material 44 into asubstantially crystalline comprising Ta₂O₅ material 50 of the desiredpattern. An example laser is a XeCl excimer laser. Example fluence forthe energy application is preferably somewhere from 0.1 J/cm² to 1.0J/cm², with a more preferred range being from 0.2 J/cm² to 0.6 J/cm².Pulse length is selected depending upon the energy to be effective toachieve the desired amorphous to crystalline phase transformation.

[0045]FIG. 12 provides one preferred example of applying a laser tosubstantially amorphous comprising Ta₂O₅ material 44 in a desiredpattern at least in part by using a masking layer having one or moreopenings therein. FIG. 13 depicts an alternate example 40 a where amasking layer is not used, with the application of the laser beingtargeted to the specific area where crystalline phase transformation isdesired.

[0046] Referring to FIG. 14, substantially amorphous comprising Ta₂O₅material 44 is removed from the substrate. In the depicted embodiment,substantially all of the remaining substantially amorphous comprisingTa₂O₅ material 44 has been removed, with the preferred technique beingchemical etching. Further, most preferred is chemical etching by any ofthe above-described techniques utilizing WF₆, and particularly underconditions effective to substantially selectively etch substantiallyamorphous comprising Ta₂O₅ material from the substrate relative tosubstantially crystalline comprising Ta₂O₅ material. Further by way ofexample only, such exposing to WF₆ can be under conditions effective toboth etch substantially amorphous Ta₂O₅ from the substrate and deposit atungsten comprising layer over the substrate during the exposing.

[0047] Yet another implementation is described with references to FIGS.15-18 of a method of forming a capacitor having a capacitor dielectricregion comprising substantially crystalline Ta₂O₅ comprising material.FIG. 15 depicts a substrate 60 comprising bulk semiconductive material62 having an insulative or other layer 64 formed thereover. A firstcapacitor electrode 66 is formed over substrate 62/64. A substantiallyamorphous comprising Ta₂O₅ comprising material 68 is formed over firstcapacitor electrode 66 and substrate 62/64.

[0048] Referring to FIG. 16, a laser has been applied to substantiallyamorphous comprising Ta₂O₅ material 68 at least over first capacitorelectrode 66 effective to transform substantially amorphous comprisingTa₂O₅ material received over first capacitor electrode 66 into asubstantially crystalline comprising Ta₂O₅ material 70 received overfirst capacitor electrode 66. Exemplary techniques for doing so includethose described above.

[0049] Referring to FIG. 17, and after the laser application, thesubstantially crystalline comprising Ta₂O₅ material and thesubstantially amorphous comprising Ta₂O₅ material have been exposed toWF₆ under conditions effective to substantially selectively etchsubstantially amorphous comprising Ta₂O₅ material from the substraterelative to substantially crystalline comprising Ta₂O₅ material 70.Exemplary and preferred techniques include those described above.

[0050] Referring to FIG. 18, a second capacitor electrode 72 is formedat least over substantially crystalline comprising Ta₂O₅ material 70received over first capacitor electrode 66. In one embodiment, theforming of the second capacitor electrode might be conducted entirelyafter the immediately above-described exposing.

[0051] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor processing method comprising: forming a substantiallyamorphous Ta₂O₅ comprising layer over a semiconductive substrate; andexposing the layer to WF₆ under conditions effective to etchsubstantially amorphous Ta₂O₅ from the substrate.
 2. The method of claim1 wherein the exposing is effective to etch substantially all of thesubstantially amorphous Ta₂O₅ comprising layer from the substrate. 3.The method of claim 1 wherein the exposing is effective to etch onlysome of the substantially amorphous Ta₂O₅ comprising layer from thesubstrate.
 4. The method of claim 1 wherein the conditions comprise atemperature of at least 350° C.
 5. The method of claim 1 wherein theconditions comprise a temperature of at least 400° C.
 6. The method ofclaim 1 wherein the conditions comprise a temperature of at least 350°C. and subatmospheric pressure.
 7. The method of claim 1 wherein thelayer consists essentially of substantially amorphous Ta₂O₅.
 8. Themethod of claim 1 wherein the exposing comprises an atmosphereconsisting essentially of WF₆.
 9. A semiconductor processing methodcomprising: forming substantially amorphous Ta₂O₅ comprising materialand substantially crystalline Ta₂O₅ comprising material over asemiconductive substrate; and exposing the layer to WF₆ under conditionseffective to etch substantially amorphous Ta₂O₅ from the substratesubstantially selective relative to the substantially crystalline Ta₂O₅comprising material.
 10. The method of claim 9 wherein the conditionscomprise a temperature of at least 350° C.
 11. The method of claim 9wherein the conditions comprise a temperature of at least 400° C. 12.The method of claim 9 wherein the exposing comprises an atmosphereconsisting essentially of WF₆.
 13. The method of claim 9 wherein theexposing comprises an atmosphere essentially void of hydrogen.
 14. Amethod of forming DRAM circuitry comprising: forming a word linetransistor over a semiconductive substrate, the word line transistorhaving a pair of source/drain regions; forming a capacitor storage nodein electrical connection with one of the source/drain regions; forming acapacitor dielectric layer over the storage node, the capacitordielectric layer comprising substantially amorphous Ta₂O₅; forming acapacitor cell electrode layer over the capacitor dielectric layer;etching through the capacitor cell electrode layer and the capacitordielectric layer over the other source/drain region; and after theetching, exposing exposed portions of the capacitor dielectric layer toWF₆ under conditions effective to etch the substantially amorphous Ta₂O₅to recess the capacitor dielectric layer relative to an overlying layer.15. The method of claim 14 wherein the overlying layer is at least thecapacitor cell electrode layer.
 16. The method of claim 14 wherein theetching does not expose the other source/drain region.
 17. The method ofclaim 14 wherein the conditions comprise a temperature of at least 350°C.
 18. The method of claim 14 wherein the conditions comprise atemperature of at least 400° C.
 19. The method of claim 14 wherein theconditions comprise a temperature of at least 350° C. and subatmosphericpressure.
 20. The method of claim 14 wherein the exposing comprises anatmosphere consisting essentially of WF₆.
 21. A method of depositing atungsten comprising layer over a substrate comprising: forming asubstantially amorphous Ta₂O₅ comprising layer over a semiconductivesubstrate; and exposing the layer to WF₆ under conditions effective toboth etch substantially amorphous Ta₂O₅ from the substrate and deposit atungsten comprising layer over the substrate during the exposing. 22.The method of claim 21 wherein the tungsten comprising layer compriseselemental tungsten.
 23. The method of claim 21 wherein the tungstencomprising layer consists essentially of elemental tungsten.
 24. Themethod of claim 21 wherein the tungsten comprising layer comprises aconductive tungsten compound.
 25. The method of claim 21 wherein thetungsten comprising layer consists essentially of a conductive tungstencompound.
 26. The method of claim 21 wherein the tungsten comprisinglayer consists essentially of elemental tungsten, a conductive tungstencompound, or mixtures thereof.
 27. The method of claim 21 wherein theconditions comprise a temperature of at least 350° C. and subatmosphericpressure.
 28. The method of claim 21 wherein the exposing is effectiveto etch substantially all of the substantially amorphous Ta₂O₅comprising layer from the substrate.
 29. The method of claim 21 whereinthe tungsten comprising layer consists essentially of elementaltungsten, a conductive tungsten compound, or mixtures thereof; and theexposing is effective to etch substantially all of the substantiallyamorphous Ta₂O₅ comprising layer from the substrate.
 30. The method ofclaim 21 wherein the exposing comprises an atmosphere comprisinghydrogen.
 31. The method of claim 30 wherein the hydrogen comprises H₂.32. A method of depositing an elemental tungsten comprising layer over asubstrate comprising: forming a substantially amorphous Ta₂O₅ comprisinglayer over a semiconductive substrate; and exposing the layer to WF₆ andhydrogen under conditions effective to both etch substantially amorphousTa₂O₅ from the substrate and deposit an elemental tungsten comprisinglayer over the substrate during the exposing.
 33. The method of claim 32wherein the hydrogen comprises H₂.
 34. The method of claim 32 whereinthe hydrogen comprises remote plasma hydrogen.
 35. The method of claim32 wherein the elemental tungsten comprising layer consists essentiallyof elemental tungsten.
 36. The method of claim 32 wherein the conditionscomprise a temperature of at least 350° C. and subatmospheric pressure.37. The method of claim 32 wherein the conditions comprise a temperatureof at least 400° C. and subatmospheric pressure.
 38. The method of claim32 wherein the exposing is effective to etch substantially all of thesubstantially amorphous Ta₂O₅ comprising layer from the substrate. 39.The method of claim 32 wherein the exposing is effective to etchsubstantially all of the substantially amorphous Ta₂O₅ comprising layerfrom the substrate, and the elemental tungsten comprising layer consistsessentially of elemental tungsten.
 40. A method of depositing a tungstennitride comprising layer over a substrate comprising: forming asubstantially amorphous Ta₂O₅ comprising layer over a semiconductivesubstrate; and exposing the layer to WF₆ and nitrogen under conditionseffective to both etch substantially amorphous Ta₂O₅ from the substrateand deposit a tungsten nitride comprising layer over the substrateduring the exposing.
 41. The method of claim 40 wherein the nitrogen isin the form of NH₃.
 42. The method of claim 40 wherein the nitrogen isin the form of N₂ plasma.
 43. The method of claim 40 wherein thenitrogen is in the form of N₂H₂.
 44. The method of claim 40 wherein theconditions comprise a temperature of at least 350° C. and subatmosphericpressure.
 45. The method of claim 40 wherein the tungsten nitridecomprising layer consists essentially of tungsten nitride.
 46. Themethod of claim 40 wherein the exposing is effective to etchsubstantially all of the substantially amorphous Ta₂O₅ comprising layerfrom the substrate, and the tungsten nitride comprising layer consistsessentially of tungsten nitride.
 47. A method of depositing a tungstensilicide comprising layer over a substrate comprising: forming asubstantially amorphous Ta₂O₅ comprising layer over a semiconductivesubstrate; and exposing the layer to WF₆ and a silane under conditionseffective to both etch substantially amorphous Ta₂O₅ from the substrateand deposit a tungsten silicide comprising layer over the substrateduring the exposing.
 48. The method of claim 47 wherein the silanecomprises SiH₄.
 49. The method of claim 47 wherein the silane comprisesdisilane.
 50. The method of claim 47 wherein the silane comprisesdichlorosilane.
 51. The method of claim 47 wherein the conditionscomprise a temperature of at least 350° C. and subatmospheric pressure.52. The method of claim 47 wherein the tungsten silicide comprisinglayer consists essentially of tungsten silicide.
 53. The method of claim47 wherein the exposing is effective to etch substantially all of thesubstantially amorphous Ta₂O₅ comprising layer from the substrate, andthe tungsten silicide comprising layer consists essentially of tungstensilicide.
 54. A method of forming a transistor gate line over asubstrate comprising: forming a gate dielectric layer over asemiconductive substrate; forming conductively doped semiconductivematerial over the gate dielectric layer; forming a substantiallyamorphous Ta₂O₅ comprising layer over the conductive semiconductivematerial; exposing the substantially amorphous Ta₂O₅ comprising layer toWF₆ under conditions effective to both remove substantially all thesubstantially amorphous Ta₂O₅ from the substrate and deposit aconductive tungsten comprising layer in its place over and in electricalconnection with the conductive semiconductive material; and after theexposing, patterning the tungsten comprising layer and the conductivesemiconductive material into a transistor gate line.
 55. The method ofclaim 54 wherein the tungsten comprising layer comprises elementaltungsten.
 56. The method of claim 54 wherein the tungsten comprisinglayer consists essentially of elemental tungsten.
 57. The method ofclaim 54 wherein the tungsten comprising layer comprises a conductivetungsten compound.
 58. The method of claim 54 wherein the tungstencomprising layer consists essentially of a conductive tungsten compound.59. The method of claim 54 wherein the tungsten comprising layerconsists essentially of elemental tungsten, a conductive tungstencompound, or mixtures thereof.
 60. The method of claim 54 wherein theconditions comprise a temperature of at least 350° C. and subatmosphericpressure.
 61. A method of forming a patterned substantially crystallineTa₂O₅ comprising material, comprising: forming a substantially amorphouscomprising Ta₂O₅ material over a substrate; applying a laser to thesubstantially amorphous comprising Ta₂O₅ material in a desired patterneffective to transform the substantially amorphous comprising Ta₂O₅material into a substantially crystalline comprising Ta₂O₅ material ofthe desired pattern; and after the applying, removing substantiallyamorphous comprising Ta₂O₅ from the substrate.
 62. The method of claim61 wherein the applying in a desired pattern is through at least oneopening formed in a masking layer.
 63. The method of claim 61 whereinthe applying is without use of a masking layer.
 64. The method of claim61 wherein the removing comprises chemical etching.
 65. A method offorming a patterned substantially crystalline Ta₂O₅ comprising material,comprising: forming a substantially amorphous comprising Ta₂O₅ materialover a substrate; applying a laser to the substantially amorphouscomprising Ta₂O₅ material in a desired pattern effective to transformthe substantially amorphous comprising Ta₂O₅ material into asubstantially crystalline comprising Ta₂O₅ material of the desiredpattern; and after the applying, exposing the substantially crystallinecomprising Ta₂O₅ material and the substantially amorphous comprisingTa₂O₅ material to WF₆ under conditions effective to substantiallyselectively etch substantially amorphous comprising Ta₂O₅ material fromthe substrate relative to substantially crystalline comprising Ta₂O₅material.
 66. The method of claim 65 wherein the applying in a desiredpattern is through at least one opening formed in a masking layer. 67.The method of claim 65 wherein the applying is without use of a maskinglayer.
 68. The method of claim 65 wherein the exposing is substantiallyvoid of hydrogen.
 69. The method of claim 65 wherein the exposing to WF₆is under conditions effective to both etch substantially amorphous Ta₂O₅from the substrate and deposit a tungsten comprising layer over thesubstrate during the exposing.
 70. A method of forming a capacitorhaving a capacitor dielectric region comprising substantiallycrystalline Ta₂O₅ comprising material, comprising: forming a firstcapacitor electrode over a substrate; forming a substantially amorphouscomprising Ta₂O₅ material over the first capacitor electrode andsubstrate; applying a laser to the substantially amorphous comprisingTa₂O₅ material at least over the first capacitor electrode effective totransform substantially amorphous comprising Ta₂O₅ material receivedover the first capacitor electrode into a substantially crystallinecomprising Ta₂O₅ material received over the first capacitor electrode;after the applying, exposing the substantially crystalline comprisingTa₂O₅ material and the substantially amorphous comprising Ta₂O₅ materialto WF₆ under conditions effective to substantially selectively etchsubstantially amorphous comprising Ta₂O₅ material from the substraterelative to substantially crystalline comprising Ta₂O₅ material; andafter the applying, forming a second capacitor electrode at least overthe substantially crystalline comprising Ta₂O₅ material received overthe first capacitor electrode.
 71. The method of claim 70 wherein theforming of the second capacitor electrode is entirely after theexposing.
 72. The method of claim 70 wherein the forming of the secondcapacitor electrode comprises the exposing, the exposing to WF₆ beingunder conditions effective to both etch substantially amorphous Ta₂O₅from the substrate and deposit a tungsten comprising layer over thesubstrate during the exposing, the tungsten comprising layer comprisingthe second capacitor electrode.
 73. The method of claim 70 wherein theapplying in a desired pattern is through at least one opening formed ina masking layer.
 74. The method of claim 70 wherein the applying iswithout use of a masking layer.